Semiconductor devices are commonly found in modern electronic products. Semiconductor devices vary in the number and density of electrical components. Discrete semiconductor devices generally contain one type of electrical component, e.g., light emitting diode (LED), small signal transistor, resistor, capacitor, inductor, and power metal oxide semiconductor field effect transistor (MOSFET). Integrated semiconductor devices typically contain hundreds to millions of electrical components. Examples of integrated semiconductor devices include microcontrollers, microprocessors, charged-coupled devices (CCDs), solar cells, and digital micro-mirror devices (DMDs).
Semiconductor devices perform a wide range of functions such as signal processing, high-speed calculations, transmitting and receiving electromagnetic signals, controlling electronic devices, transforming sunlight to electricity, and creating visual projections for television displays. Semiconductor devices are found in the fields of entertainment, communications, power conversion, networks, computers, and consumer products. Semiconductor devices are also found in military applications, aviation, automotive, industrial controllers, and office equipment. In particular, power MOSFETs are commonly used in electronic circuits, such as communication systems and power supplies, as electric switches to enable and disable the conduction of relatively large currents in DC to DC converter applications.
A power MOSFET device includes a large number of MOSFET cells or individual transistors that are connected in parallel and distributed across a surface of a semiconductor die. Power MOSFET devices are typically used as electronic switches to control power flow to a circuit. A control signal at a gate terminal of the power MOSFET controls whether current flows through the MOSFET between a drain terminal and source terminal of the MOSFET. The conduction path between the drain terminal and source terminal of a MOSFET is wired in series with a circuit to be switched, so that when the MOSFET is off, i.e., the MOSFET limits current between the source and drain terminals, current is also limited through the switched circuit. When the MOSFET is on, current flows through the MOSFET and the switched circuit to power the switched circuit.
Power MOSFETs waste energy through switching power loss and conduction power loss. Conduction losses are proportional to the effective resistance of the conduction path from the drain terminal to the source terminal when the transistor is turned on (RDSON), i.e., the resistance exhibited for current flowing to powered circuits. A MOSFET with a higher RDSON will absorb more energy, and generate more heat, as current flows through the MOSFET to the circuit being powered.
Switching losses are proportional to the switching frequency and internal parasitic capacitance, most significantly gate to drain capacitance (Cgd). A higher Cgd indicates more energy is used in order to switch a MOSFET from on to off, or from off to on. The gate charge of a MOSFET (Qg) indicates the amount of charge supplied to the gate terminal to switch a MOSFET on. Qg is proportional to the Cgd of a MOSFET. Frequency of switching increases switching loss because the power loss experienced during a single switch cycle is experienced more often.
One goal of power MOSFET manufacturers is to produce power MOSFET devices with lower conduction losses. Lower conduction loss, i.e., lower RDSON, reduces the amount of energy absorbed by the power MOSFET when the MOSFET is conducting. When a power MOSFET absorbs energy, more energy is required to power the circuit as a whole. In addition, the absorbed energy is released by the MOSFET as thermal energy which may need to be dissipated away from the MOSFET using a heatsink, or other method, to prevent damage to the MOSFET.
Another goal of power MOSFET manufacturers is to produce power MOSFET devices which can switch higher voltage power signals. In order to switch a power signal of a certain voltage level, a power MOSFET sustains an equivalent voltage between the drain terminal and source terminal when off. The maximum voltage level which a power MOSFET can be used with is determined by the BVdss value of the MOSFET, or the maximum blocking voltage of the MOSFET between drain and source.
Conventional power MOSFETs use a vertical or trench configuration due to a characteristically low RDSON. However, trench power MOSFETS commonly exhibit high Cgd and Qg, which results in a higher switching power loss. The trench MOSFET structure can be modified to improve Cgd, but at the expense of significantly increased manufacturing complexity. On the other hand, lateral double-diffused MOSFETs (LDMOS) offer inherently lower Qg than vertical double-diffused power MOSFETS (VDMOS), which reduces switching power loss, but have a higher RDSON, which increases conduction power loss.
Conventional power MOSFETs include a lightly doped drain (LDD), or drift, region to support a higher BVdss. FIG. 1a illustrates a conventional N-channel LDMOS power MOSFET cell 10. MOSFET cell 10 is formed from P-doped base substrate material 12, and includes P-channel area 14, P+ source contact region 16, N+ source contact region 18, and N+ drain contact region 20. Gate dielectric 22 is formed over base substrate material 12, and polysilicon (poly) gate 24 is formed over the gate dielectric. LDD region 26 is lightly doped with an N-type dopant and runs from an area under poly gate 24 to N+ drain contact region 20.
The doping concentration of LDD region 26 has an inverse relationship to BVdss, but also has an inverse relationship to RDSON. Lowering the doping concentration of LDD region 26 results in MOSFET cell 10 having a higher BVdss, but also a higher RDSON. The LDD region supports a high BVdss of MOSFET cell 10 by providing additional area between a voltage applied to the MOSFET at N+ drain contact region 20 and the channel under poly gate 24. The additional area, combined with a lower doping concentration, provided by LDD region 26 spreads out a depletion region between the applied voltage at N+ drain contact region 20 and the channel under poly gate 24 to produce a lower magnitude electric field for a given voltage, thereby increasing BVdss. While LDD region 26 results in a reduced electric field, fixed potential points exist at the edge of poly gate 24 and at N+ drain contact region 20 which cause the electric field to peak at each end of the LDD region.
A depletion region exists at the boundary between LDD region 26 and base substrate material 12. As a voltage applied to N+ drain contact region 20 rises, the depletion region between LDD region 26 and base substrate material 12 grows. The doping of LDD region 26 is such that LDD region 26 will be fully depleted of charge carriers prior to MOSFET cell 10 breaking down. Base substrate material 12 is more lightly doped than LDD region 26, and the depletion region extends further into the base substrate material than the size of the LDD region.
Power MOSFET manufacturers want to create devices with lower RDSON, and have developed superjunction structures used as the drift region of a MOSFET cell, instead of an LDD region, to reduce RDSON. FIG. 1b illustrates MOSFET cell 30 which utilizes a superjunction drift region. MOSFET cell 30 is formed in a similar process to MOSFET cell 10 in FIG. 1a, but N-doped stripes 32 and P-doped stripes 34 are formed to replace LDD region 26. N-doped stripes 32 include a width Wn. P-doped stripes 34 include a width Wp. Stripes 32 and 34 include a junction depth into base substrate material 12, Xj, which is the same for each stripe. Stripes 32 and 34 are doped as heavily as possible while still fully depleting prior to the breakdown of MOSFET cell 30. A superjunction is used to provide as much heavily doped area between N+ drain contact region 20 and poly gate 24 as possible.
Superjunctions remove the relationship between BVdss and doping concentration, as is the case with MOSFET cell 10 which uses LDD region 26. A higher doping concentration is used in the superjunction as compared to LDD region 26, resulting in lower RDSON. MOSFETs designed with a superjunction improve the RDSON of the MOSFET without a significant increase in Qg, resulting in a net reduction of total power loss.
Superjunctions maintain a high BVdss despite a high doping concentration by replacing the depletion region between LDD region 26 and base substrate material 12 with a plurality of depletion regions between each adjacent N-doped stripe 32 and P-doped stripe 34. Stripes 32 and 34 deplete each other instead of base substrate material 12, therefore the electric field of the superjunction is oriented laterally. The doping concentrations of stripes 32 and 34 are calibrated such that the stripes fully deplete prior to breakdown of MOSFET cell 30, similarly to LDD region 26 in MOSFET cell 10. After stripes 32 and 34 are fully depleted, the voltage at drain contact region 20 is supported by the length, Lsj, of the superjunction. When the superjunction is fully depleted, the electric field from applied voltage at N+ drain contact 20 to poly gate 24 is oriented lengthwise through the superjunction. Making stripes 32 and 34 longer increases BVdss by stretching the electric fields over a longer distance, reducing the magnitude of the electric fields.
N-doped stripes 32 and P-doped stripes 34 include strong electric fields at the depletion regions between the stripes. In addition, as with LDD region 26, inherently stronger electric fields exist under the edge of poly gate 24 and at N+ drain contact region 20. The strong electric fields of the depletion regions between N-doped stripes 32 and P-doped stripes 34 combine with the electric field peaks at the edge of poly gate 24 and N+ drain contact region 20 to create an electric field strong enough to cause breakdown of MOSFET cell 30 at a lower voltage than is desired.
The strong electric fields of the superjunction depletion regions combining with the electric field peaks at poly gate 24 and N+ drain contact region 20 also creates hot carriers. Hot carriers are electrons or holes which reach an energy high enough to be injected into dielectric layer 22. Hot carriers trapped in dielectric layer 22 increase leakage current through the dielectric layer, and eventually lead to a short circuit between poly gate 24 and base substrate material 12. Hot carriers trapped in dielectric layer 22 also create an electric field in base substrate material 12 and disrupt the charge balance of the superjunction. BVdss is reduced by hot carriers affecting the charge balance of the superjunction.
Thinner stripes 32 and 34 are doped at a higher concentration while still fully depleting at the same voltage as thicker superjunction stripes. In addition, using thinner stripes 32 and 34 does not reduce the total conduction area through N-doped stripes 32 when MOSFET cell 30 is on because the area through the N-doped stripes is approximately half of the total width of the MOSFET regardless of the width of each individual stripe. Therefore, thinner stripes 32 and 34 benefit total RDSON without hurting BVdss.
Forming deeper stripes 32 and 34 reduces RDSON by providing more conduction area for current through MOSFET cell 30 when the MOSFET is on. However, fabricating a deep superjunction LDMOS requires high energy ion implants, a trench etch with sidewall implant, or a multi-step silicon epitaxy. Each option for fabricating a deep superjunction presents challenges in terms of cost, process engineering, and process equipment capability. Fabricating a deep junction with narrow stripe widths using conventional implant and well techniques is challenging because the thermal diffusion processes required to form deep wells cause the N and P stripes to diffuse together, which reduces or eliminates the benefits of a superjunction. Using a high resolution photoresist is challenging because as resolution of the photoresist is increased, thickness is decreased. The thin photoresist required for high resolution ion implants does not easily block the high energy ion implants required to form deep junctions.
FIG. 1c illustrates the theoretical relationship between stripe width, junction depth, and RDSON. FIG. 1c shows that RDSON is reduced as stripe width (Wn and Wp) is reduced, and as junction depth (Xj) is increased.